Comparison of iFinFET and Nanosheet FET 3 nm-Node Transistor Designs
To continue the historical gains in information technology processing power due to Moore’s Law, semiconductor device manufacturers are adopting complex gate-all-around (GAA) Nanosheet transistor structures for the newest integrated circuit technology nodes. While these Nanosheet structures offer enhanced device performance at the < 12 nm gate lengths required to meet these density targets, they are much more difficult and costly to manufacture than the current state-of-the-art FinFET device architecture. In this talk, I will introduce an evolutionary structure called the inserted-oxide FinFET (iFinFET), which can provide comparable performance and scalability to the Nanosheet FET with a simpler manufacturing process flow. I will show through device simulations that despite its inferior electrostatic integrity, iFinFET has comparable performance and scalability to Nanosheet technologies due to reduced gate capacitance and larger effective channel width. Moreover, I will discuss iFinFET fabrication methods based on inserted oxygen monolayers and Silicon/Silicon-Germanium superlattices that lack the difficult channel release and high-aspect etching steps in the nanosheet fabrication process.
Lars Tatum is a Ph.D. student in Electrical Engineering and Computer Sciences at UC Berkeley, where he works on semiconductor device and process technologies for compact integrated systems in the research group of Professor Tsu-Jae King Liu. Previously, he received a B.S. in Electrical Engineering at the University of Florida in 2019, where he worked on advanced device simulation techniques in the research group of Professor Mark Law.